#ifndef STM32F1_TIMER_H_
#define STM32F1_TIMER_H_

#include "iodef.h"

typedef struct {
        __IO uint16_t CR1;
        uint16_t  RESERVED0;
        __IO uint16_t CR2;
        uint16_t  RESERVED1;
        __IO uint16_t SMCR;
        uint16_t  RESERVED2;
        __IO uint16_t DIER;
        uint16_t  RESERVED3;
        __IO uint16_t SR;
        uint16_t  RESERVED4;
        __IO uint16_t EGR;
        uint16_t  RESERVED5;
        __IO uint16_t CCMR1;
        uint16_t  RESERVED6;
        __IO uint16_t CCMR2;
        uint16_t  RESERVED7;
        __IO uint16_t CCER;
        uint16_t  RESERVED8;
        __IO uint16_t CNT;
        uint16_t  RESERVED9;
        __IO uint16_t PSC;
        uint16_t  RESERVED10;
        __IO uint16_t ARR;
        uint16_t  RESERVED11;
        __IO uint16_t RCR;
        uint16_t  RESERVED12;
        __IO uint16_t CCR1;
        uint16_t  RESERVED13;
        __IO uint16_t CCR2;
        uint16_t  RESERVED14;
        __IO uint16_t CCR3;
        uint16_t  RESERVED15;
        __IO uint16_t CCR4;
        uint16_t  RESERVED16;
        __IO uint16_t BDTR;
        uint16_t  RESERVED17;
        __IO uint16_t DCR;
        uint16_t  RESERVED18;
        __IO uint16_t DMAR;
        uint16_t  RESERVED19;
}timer_reg_t;

#define TIM_CR1_CEN             _BIT(0)
#define TIM_CR1_UDIS            _BIT(1)
#define TIM_CR1_URS             _BIT(2)
#define TIM_CR1_OPM             _BIT(3)
#define TIM_CR1_DIR             _BIT(4)

#define TIM_CR1_CMS_MASK        _VALUE(5, 0x3)
#define TIM_CR1_CMS_EDGE        _VALUE(5, 0x0)
#define TIM_CR1_CMS_CENTER1     _VALUE(5, 0x1)
#define TIM_CR1_CMS_CENTER2     _VALUE(5, 0x2)
#define TIM_CR1_CMS_CNETER3     _VALUE(5, 0x3)

#define TIM_CR1_ARPE            _BIT(7)

#define TIM_CR1_CKD_MASK        _VALUE(8, 0x3)
#define TIM_CR1_CKD_MUL1        _VALUE(8, 0x0)
#define TIM_CR1_CKD_MUL2        _VALUE(8, 0x1)
#define TIM_CR1_CKD_MUL4        _VALUE(8, 0x2)

#define TIM_CR2_CCPC            _BIT(0)
#define TIM_CR2_CCUS            _BIT(2)
#define TIM_CR2_CCDS            _BIT(3)

#define TIM_CR2_MMS_MASK        _VALUE(4, 0x7)
#define TIM_CR2_MMS_RESET       _VALUE(4, 0x0)
#define TIM_CR2_MMS_ENABLE      _VALUE(4, 0x1)
#define TIM_CR2_MMS_UPDATE      _VALUE(4, 0x2)
#define TIM_CR2_MMS_COMP_PLUS   _VALUE(4, 0x3)
#define TIM_CR2_MMS_COMP_OC1    _VALUE(4, 0x4)
#define TIM_CR2_MMS_COMP_OC2    _VALUE(4, 0x5)
#define TIM_CR2_MMS_COMP_OC3    _VALUE(4, 0x6)
#define TIM_CR2_MMS_COMP_OC4    _VALUE(4, 0x7)

#define TIM_CR2_TI1S            _BIT(7)
#define TIM_CR2_OIS1            _BIT(8)
#define TIM_CR2_OIS1N           _BIT(9)
#define TIM_CR2_OIS2            _BIT(10)
#define TIM_CR2_OIS2N           _BIT(11)
#define TIM_CR2_OIS3            _BIT(12)
#define TIM_CR2_OIS3N           _BIT(13)
#define TIM_CR2_OIS4            _BIT(14)

#define TIM_SMCR_SMS_MASK       _VALUE(0, 0x7)
#define TIM_SMCR_SMS_DISABLE    _VALUE(0, 0x0)
#define TIM_SMCR_SMS_ENCODER1   _VALUE(0, 0x1)
#define TIM_SMCR_SMS_ENCODER2   _VALUE(0, 0x2)
#define TIM_SMCR_SMS_ENCODER3   _VALUE(0, 0x3)
#define TIM_SMCR_SMS_RESET      _VALUE(0, 0x4)
#define TIM_SMCR_SMS_GATED      _VALUE(0, 0x5)
#define TIM_SMCR_SMS_TRIGGER    _VALUE(0, 0x6)
#define TIM_SMCR_SMS_EXTCLK1    _VALUE(0, 0x7)

#define TIM_SMCR_TS_MASK        _VALUE(4, 0x7)
#define TIM_SMCR_TS_ITR0        _VALUE(4, 0x0)
#define TIM_SMCR_TS_ITR1        _VALUE(4, 0x1)
#define TIM_SMCR_TS_ITR2        _VALUE(4, 0x2)
#define TIM_SMCR_TS_ITR3        _VALUE(4, 0x3)
#define TIM_SMCR_TS_TI1F_ED     _VALUE(4, 0x4)
#define TIM_SMCR_TS_TI1FP1      _VALUE(4, 0x5)
#define TIM_SMCR_TS_TI1FP2      _VALUE(4, 0x6)
#define TIM_SMCR_TS_ETRF        _VALUE(4, 0x7)

#define TIM_SMCR_MSM            _BIT(7)

#define TIM_SMCR_ETF_MASK       _VALUE(8, 0xF)
#define TIM_SMCR_ETF(n)         _VALUE(8, (n))

#define TIM_SMCR_ETPS_MASK      _VALUE(12, 0x3)
#define TIM_SMCR_ETPS_OFF       _VALUE(12, 0x0)
#define TIM_SMCR_ETPS_DIV2      _VALUE(12, 0x1)
#define TIM_SMCR_ETPS_DIV4      _VALUE(12, 0x2)
#define TIM_SMCR_ETPS_DIV8      _VALUE(12, 0x3)

#define TIM_SMCR_ECE            _BIT(14)
#define TIM_SMCR_ETP            _BIT(15)

#define TIM_DIER_UIE            _BIT(0)
#define TIM_DIER_CC1IE          _BIT(1)
#define TIM_DIER_CC2IE          _BIT(2)
#define TIM_DIER_CC3IE          _BIT(3)
#define TIM_DIER_CC4IE          _BIT(4)
#define TIM_DIER_COMIE          _BIT(5)
#define TIM_DIER_TIE            _BIT(6)
#define TIM_DIER_BIE            _BIT(7)
#define TIM_DIER_UDE            _BIT(8)
#define TIM_DIER_CC1DE          _BIT(9)
#define TIM_DIER_CC2DE          _BIT(10)
#define TIM_DIER_CC3DE          _BIT(11)
#define TIM_DIER_CC4DE          _BIT(12)
#define TIM_DIER_COMDE          _BIT(13)
#define TIM_DIER_TDE            _BIT(14)

#define TIM_SR_UIF              _BIT(0)
#define TIM_SR_CC1IF            _BIT(1)
#define TIM_SR_CC2IF            _BIT(2)
#define TIM_SR_CC3IF            _BIT(3)
#define TIM_SR_CC4IF            _BIT(4)
#define TIM_SR_COMIF            _BIT(5)
#define TIM_SR_TIF              _BIT(6)
#define TIM_SR_BIF              _BIT(7)
#define TIM_SR_CC1OF            _BIT(9)
#define TIM_SR_CC2OF            _BIT(10)
#define TIM_SR_CC3OF            _BIT(11)
#define TIM_SR_CC4OF            _BIT(12)

#define TIM_EGR_UG              _BIT(0)
#define TIM_EGR_CC1G            _BIT(1)
#define TIM_EGR_CC2G            _BIT(2)
#define TIM_EGR_CC3G            _BIT(3)
#define TIM_EGR_CC4G            _BIT(4)
#define TIM_EGR_COMG            _BIT(5)
#define TIM_EGR_TG              _BIT(6)
#define TIM_EGR_BG              _BIT(7)

#endif /* STM32F1_TIMER_H_ */
